In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. For example, a dual port (DP) SRAM device allows parallel operation, such as 1R (read) 1W (write), or 2R (read) in one cycle, and therefore has higher bandwidth than a single port SRAM. In advanced technologies, low loading and high speed of the cell structure are important factors in embedded memory and SOC products. The thin style SRAM cell structure with short bit-line (BL) provides better performance on BL RC delay. However, the thin style cell structure suffers some problems including data node leakage, devices matching of pull-down (PD)/pass-gate (PG) devices and current crowding, etc. Special operation mode (parallel operation) of the DP SRAM requests more pull down drive capability to cover two-ports of the ON operation mode. This further requires double beta ratio setting for static noise margin (SNM). As such, the PD device width will be around 2× from the single-port cell. To consider reasonable SNM, the device width ratio between PD and PG is around 2˜4 on the DP cell. This results in a L-shape or T-shape layout of the drain node of the PD device, and therefore may suffer the above problems. Another issue associated with the above structure is that one of half node uses the gate layer as intra-cell local interconnect to handle a current path between the source node of a PG transistor to the drain node of a PD transistor. This high resistance will dramatically impact the cell performance (such as cell current balance, read speed and write capability) when the gate layer resistance continuously increases from generation to generation.